The present invention relates to semiconductor transistors and has particular application to thin film polycrystaline transistors.
Herein the abbreviation ID is used to refer to the transistor drain current, VG is used to refer to the transistor gate voltage generally, VDS is used to refer to the transistor drain to source voltage, and VGS is used to refer to the transistor gate to source voltage. Furthermore, herein the word xe2x80x9conxe2x80x9d, such as in the description of one film or layer being xe2x80x9cformed on anotherxe2x80x9d is not intended to require direct contact between the two layers. That is, for example, it should not be interpreted as excluding arrangements in which another layer or film is interposed between the one layer which is formed xe2x80x9conxe2x80x9d the other.
Unlike the output characteristics (ID-VDS) of single crystal MOSFETs, a saturation regime is not observed, for example, in a polycrystaline silicon thin film transistor. Instead, as shown in FIG. 1, when the device is operating above the so-called pinch-off level, generally when VDS greater than VGS, high electric fields are formed near the drain and this results in so called impact ionisation. The result is an increase in drain current ID which is often referred to as the kink effect. This effect increases power dissipation and degrades the switching characteristics in digital circuits, whilst reducing the maximum obtainable gain as well as the common mode rejection ratio in analogue circuits.
The kink effect is also affected by the so-called parasitic bipolar effect, which is well known in silicon-on-insulator (SOI) devices. This occurs when electron-hole pairs are generated with impact ionisation at high electric fields near the drain, resulting in the holes drifting towards the source and causing a potential barrier lowering at the source junction. This effect also occurs in polysilicon thin film transistors and is due to the fact that the thin film active layer acts as the base of a bipolar transistor.
Against this background and with a view to providing an improved semiconductor transistor, in a first aspect the present invention provides a method of manufacturing a semiconductor transistor having a gate, a source and a drain, comprising the steps of: providing a semiconductor layer in which the source and drain are to be formed; forming a gate insulating layer on the semiconductor layer; forming a split gate electrode on the gate insulating layer; and using the split gate electrode as a mask in the doping of a portion of the semiconductor layer between the source and the drain of the final transistor.
According to a second aspect of the present invention there is provided a semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the gate electrode is split, the active layer has a doped region located between the source and the drain and aligned with the split in the gate electrode, and the gate electrode is aligned with the drain so as not to overlap the drain.